Current VLSI systems are built according to a System-on-Chip (SoC) concept. System-on-Chip functionalities are the result of the cooperation between several simple modules that are generally selected by the designer from a preexisting library.
The designer role is to map the System-on-Chip functions onto the modules of the library. However, effective communication and interconnection systems are needed to meet suitable performances for the designed SoC system, and in particular, to provide effective communications between the modules of the system.
As system complexity increases, on-chip communications becomes more critical, and current on-chip communication systems tend to become complex arranged infrastructures. In addition, it is usually predicted that, in the next few years, system-on-chips will include hundreds of communicating blocks running at many GHz. Such systems are known as multiprocessor systems-on-chips (MP-SoCs).
Researchers have recently proposed the Network-on-Chip concept (NoC) to overcome the limitations relating to the huge efforts necessary to adequately design on-chip communication systems, even for the MP-SoCs systems. An NoC provides scalable and flexible communication architectures with suitable performances. Moreover, an NoC provides the SoC architects with a tool for designing on-chip communication systems quickly, thus increasing productivity and reducing time to market.
The NoC is a non-centralized architecture that is intended to be physically implemented as a distributed communication infrastructure. NoCs are nevertheless based on a packet switch communication concept and are mainly composed of three NoC modules, namely a router (R), a Network Interface (NI), and a link.
The synchronization issues in a NoC architecture imposes a large scalability limitation, and approaches at the architecture level ready to be industrialized in the near future need to be provided to fully enable NoC deployment. Currently, most of the NoC approaches are fully synchronous so that all the modules have the same clock frequency and data is transferred using traditional synchronous protocols.
Distributing a same clock signal over the entire NoC structure is a big issue. As a matter of fact, a NoC structure is a distributed architecture spread on a chip in such a manner so as to reduce the wiring length of the links. Accordingly, distributing a same clock signal for the entire NoC structure is costly in terms of time or in terms of area since buffers are needed to overcome phase shifting in different areas of the structure.
An alternative approach to some NoC architectures is to build asynchronous links. However, at present, asynchronous communications implies intolerable overhead in terms of wires and area, as well as latency. Moreover, asynchronous design techniques are not supported by standard design industrial EDA flows.